ADAU1361BCPZ-R7 datasheet(29/78 Pages) AD

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Data Sheet

ADAU1361

RECORD SIGNAL PATH

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Rev. E | 29 of 78

boost provides two different voltage biases: 0.65 × AVDD or 0.90 ×

AVDD. When enabled, the high perfor-mance bit increases supply

current to the microphone bias circuit to decrease rms input noise.

The MICBIAS pin can also be used to cleanly supply voltage to

digital microphones or analog microphones with separate power

supply pins.

ANALOG-TO-DIGITAL CONVERTERS

The ADAU1361 uses two 24-bit Σ-Δ analog-to-digital con-verters

(ADCs) with selectable oversampling ratios of 64× or 128× (select-

ed by Bit 3 in Register R17, Address 0x4017).

ADC Full-Scale Level

The full-scale input to the ADCs (0 dBFS) depends on AVDD. At

AVDD = 3.3 V, the full-scale input level is 1.0 V rms. This full-scale

analog input outputs a digital signal at −1.38 dBFS. This gain offset

is built into the ADAU1361 to prevent clipping. The full-scale input

level scales linearly with the level of AVDD.

For single-ended and pseudo-differential signals, the full-scale val-

ue corresponds to the signal level at the pins, 0 dBFS.

The full differential full-scale input level is measured after the

differential amplifier, which corresponds to −6 dBFS at each pin.

Signal levels above the full-scale value cause the ADCs to clip.

Digital ADC Volume Control

The digital ADC volume can be attenuated using Register R20 (left

input digital volume register, Address 0x401A) and Register R21

(right input digital volume register, Address 0x401B).

High-Pass Filter

By default, a high-pass filter is used in the ADC path to remove

dc offsets; this filter can be enabled or disabled in Register R19

(ADC control register, Address 0x4019). At fS = 48 kHz, the corner

frequency of this high-pass filter is 2 Hz.

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