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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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4571 데이터시트(PDF) 11 Page - Renesas Technology Corp |
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4571 데이터시트(HTML) 11 Page - Renesas Technology Corp |
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11 / 126 page  Rev.1.02 May 25, 2007 Page 11 of 124 REJ03B0179-0102 4571 Group Fig 6. Port block diagram (4) Key-on wakeup input SNZI0 instruction (Note 1) L11 0 1 Edge detection circuit Level detection circuit P20/INT0 I13 I12 Falling 0 1 Rising L10 I11 0 1 One-sided edge detection circuit Both edges detection circuit Skip EXF0 External 0 interrupt Timer 1 count start synchronization circuit input (Note 2) (Note 3) Note 1: This symbol represents a parasitic diode on the port. 2: When IX2= 0(X=0 or 1) is 0, “L” level is detected. When IX2 is 1, “H” level is detected. 3: When IX2 is 0, falling edge is detected. When IX2 is 1, rising edge is detected. (Note 1) Key-on wakeup input SNZI1 instruction (Note 1) L13 0 1 Edge detection circuit Level detection circuit P21/INT1 I23 I22 Falling 0 1 Rising L12 I21 0 1 One-sided edge detection circuit Both edges detection circuit Skip EXF1 External 1 interrupt (Note 2) (Note 3) (Note 1) |
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