4559 datasheet(4/148 Pages) RENESAS

4 / 148 page

Rev.1.04

Aug 23, 2007

Page 4 of 146

REJ03B0188-0104

4559 Group

PERFORMANCE OVERVIEW

Table 2

Performance overview

Parameter

Function

Number of basic instructions

135

Minimum instruction execution time

0.5

µs (Oscillation frequency 6 MHz: high-speed through mode)

Memory sizes

ROM

6144 words

× 10 bits

RAM

288 words

× 4 bits (including LCD display RAM 32 words × 4 bits)

I/O port

−D5

I/O

(Input is

examined by

skip decision.)

Six independent I/O ports.

The output structure can be switched by software.

Port D5 is also used as INT pin.

D6, D7

Output

Two independent output ports.

Ports D6 and D7 are also used as XCIN and XCOUT, respectively.

P00

−P03

I/O

4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can

be switched by software.

Ports P00

−P03 are also used as SEG16−SEG19, respectively.

P10

−P13

I/O

4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can

be switched by software.

Ports P10

−P13 are also used as SEG20−SEG23, respectively.

P20

−P23

I/O

4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can

be switched by software.

Ports P20

−P23 are also used as SEG24−SEG27, respectively.

P30

−P33

I/O

4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can

be switched by software.

Ports P30

−P33 are also used as SEG28−SEG31, respectively.

Output

1-bit output; Port C is also used as CNTR pin.

Timer

Timer 1

8-bit timer with a reload register and carrier wave output auto-control function,

and has an event counter.

Timer 2

8-bit timer with two reload registers and carrier wave generation function.

Timer 3

16-bit timer, fixed dividing frequency (timer for clock count)

Timer LC

4-bit programmable timer with a reload register (for LCD clock generating)

Watchdog timer

16-bit timer, fixed dividing frequency (timer for monitor)

LCD control circuit

Selective bias value

1/2, 1/3 bias

Selective duty value

2, 3, 4 duty

Common output

Segment output

Internal resistor for power

supply

× 3, 2r × 2, r × 3, r × 2 (r = 100 kΩ, (Ta = 25 °C, Typical value))

Voltage drop

detection circuit

Reset occurrence

Typ. 1.7 V (Ta=25 °C)

Reset release

Typ. 1.8 V (Ta=25 °C)

Skip occurrence

Typ. 2.0 V (Ta=25 °C)

Power-on reset circuit

Built-in

Interrupt

Source

4 sources (one for external, three for timers)

Nesting

1 level

Subroutine nesting

8 levels

Device structure

CMOS silicon gate

Package

52-pin plastic molded LQFP (PLQP0052JA-A)

Operating temperature range

-20 to 85 °C

Power source voltage

1.8 to 5.5 V (It depends on operation source clock, oscillation frequency and

operation mode)

Power

dissipation

(Typ. value)

At active mode

0.3 mA (Ta = 25 °C, VDD

= 3 V, f(XIN) = 4 MHz, f(XCIN) = stop, f(RING) = stop,

f(STCK) = f(XIN)/8

At clock operating mode

µA (Ta = 25 °C, VDD = 3 V, f(XCIN) = 32 kHz)

At RAM back-up

0.1

µA (Ta = 25 °C, VDD = 5 V, output transistor is cut-off state)

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