FALXT972MCCA4 datasheet(31/92 Pages) INTEL

31 / 92 page

Intel

® LXT972M Single-Port 10/100 Mbps PHY Transceiver

Datasheet

Document Number: 302875-005

Revision Date: 27-Oct-2005

5.4.1

MDIO Control Mode and Hardware Control Mode

In the MDIO Control mode, the LXT972M Transceiver reads the Hardware Control Interface pins

to set the initial (default) values of the MDIO registers. Once the initial values are set, bit control

reverts to the MDIO interface.

The following modes are available using MDIO Control.

• Force network link operation to:

— 100BASE-TX, Full-Duplex

— 100BASE-TX, Half-Duplex

— 10BASE-T, Full-Duplex

— 10BASE-T, Half-Duplex

• Allow auto-negotiation/parallel-detection

On power-up or hardware reset, the LXT972M Transceiver reads the Hardware Control Interface

pins and sets the MDIO registers accordingly.

The following modes are available using the Hardware Control:

• Auto-negotiation-enabled advertising, either:

— 10/100 BASE-T Full/Half Duplex

— 10/100 BASE-T Half Duplex

• LXT972M Transceiver device ID enable

• Link Hold-off

When the network link is forced to a specific configuration, the LXT972M Transceiver

immediately begins operating the network interface as commanded. When auto-negotiation is

enabled, the LXT972MTransceiver begins the auto-negotiation/parallel-detection operation.

5.4.2

Reduced-Power Modes

This section discusses the LXT972M Transceiver reduced-power modes.

5.4.2.1

Software Power Down

Software power-down control is provided by Register bit 0.11 in the Control Register. (See

Table 41 on page 76.) During soft power-down, the following conditions are true:

• The network port is shut down.

• The MDIO registers remain accessible.

5.4.3

Reset for Intel® LXT972M Transceiver

The LXT972M Transceiver provides both hardware and software resets, each of which manage

differently the configuration control of auto-negotiation, speed, and duplex-mode selection.

For a software reset, Register bit 0.15 = 1. For register bit definitions used for software reset, see

Table 41, “Control Register - Address 0, Hex 0” on page 76.

FALXT972MCCA4 데이터시트(PDF) 31 Page - Intel Corporation

FALXT972MCCA4 데이터시트(HTML) 31 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

데이터시트 다운로드

링크 URL