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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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FALXT972MCCA4 데이터시트(PDF) 38 Page - Intel Corporation |
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FALXT972MCCA4 데이터시트(HTML) 38 Page - Intel Corporation |
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38 / 92 page  Intel ® LXT972M Single-Port 10/100 Mbps PHY Transceiver 38 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 5.6.2 Transmit Enable The MAC must assert TX_EN the same time as the first nibble of preamble and de-assert TX_EN after the last nibble of the packet. 5.6.3 Receive Data Valid The LXT972M Transceiver asserts RX_DV when it receives a valid packet. Timing changes depend on line operating speed: • For 100BASE-TX links, RX_DV is asserted from the first nibble of preamble to the last nibble of the data packet. • For 10BASE-T links, the entire preamble is truncated. RX_DV is asserted with the first nibble of the Start of Frame Delimiter (SFD) “5D” and remains asserted until the end of the packet. Figure 9. Clocking for Link Down Clock Transition Any Clock 2.5 MHz Clock Clock transition time does not exceed 2X the nominal clock period: 10 Mbps = 2.5 MHz 100 Mbps = 25 MHz Link-Down Condition/Auto-Negotiate Enabled RX_CLK TX_CLK B3503-01 |
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