FALXT972MCCA4 datasheet(50/92 Pages) INTEL

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Intel

® LXT972M Single-Port 10/100 Mbps PHY Transceiver

Datasheet

Document Number: 302875-005

Revision Date: 27-Oct-2005

5.8

10 Mbps Operation

The LXT972M Transceiver operates as a standard 10BASE-T transceiver and supports standard

10 Mbps functions. During 10BASE-T operation, the LXT972M Transceiver transmits and

receives Manchester-encoded data across the network link. When the MAC is not actively

transmitting data, the LXT972M Transceiver drives link pulses onto the line.

In 10BASE-T mode, the polynomial scrambler/de-scrambler is inactive. Manchester-encoded

signals received from the network are decoded by the LXT972M Transceiver and sent across the

MII to the MAC.

Note:

5.8.1

10BASE-T Preamble Handling

The LXT972M Transceiver offers two options for preamble handling, selected by Register bit 16.5.

• In 10BASE-T mode when Register bit 16.5 = 0, the LXT972M Transceiver strips the entire

preamble off of received packets. CRS is asserted coincident with the start of the preamble.

RX_DV is held Low for the duration of the preamble. When RX_DV is asserted, the very first

two nibbles driven by the LXT972M Transceiver are the SFD “5D” hex followed by the body

of the packet.

• In 10BASE-T mode when Register bit 16.5 = 1, the LXT972M Transceiver passes the

preamble through the MII and asserts RX_DV and CRS simultaneously. (In 10BASE-T

loopback, the LXT972M Transceiver loops back whatever the MAC transmits to it, including

the preamble.)

5.8.2

10BASE-T Carrier Sense

For 10BASE-T links, CRS assertion is based on reception of valid preamble, and CRS de-assertion

is based on reception of an end-of-frame (EOF) marker. Register bit 16.7 allows CRS de-assertion

to be synchronized with RX_DV de-assertion. For details, see Table 51, “Configuration Register -

Address 16, Hex 10” on page 84.

5.8.3

10BASE-T Dribble Bits

The LXT972M Transceiver handles dribble bits in all modes. If one to four dribble bits are

received, the nibble is passed across the MII, padded with ones if necessary. If five to seven

dribble bits are received, the second nibble is not sent to the MII bus.

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