| 전자부품 데이터시트 검색엔진 |
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PIC18F44J10-E/ML 데이터시트(PDF) 219 Page - Microchip Technology |
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PIC18F44J10-E/ML 데이터시트(HTML) 219 Page - Microchip Technology |
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219 / 358 page ![]() © 2007 Microchip Technology Inc. Preliminary DS39682C-page 217 PIC18F45J10 FAMILY 17.7 A/D Conversions Figure 17-4 shows the operation of the A/D converter after the GO/DONE bit has been set and the ACQT2:ACQT0 bits are cleared. A conversion is started after the following instruction to allow entry into Sleep mode before the conversion begins. Figure 17-5 shows the operation of the A/D converter after the GO/DONE bit has been set and the ACQT2:ACQT0 bits are set to ‘010’ and selecting a 4 TAD acquisition time before the conversion starts. Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D Result register pair will NOT be updated with the partially completed A/D conversion sample. This means the ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers). After the A/D conversion is completed or aborted, a 2TAD wait is required before the next acquisition can be started. After this wait, acquisition on the selected channel is automatically started. FIGURE 17-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0) FIGURE 17-5: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD) Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD11 Set GO/DONE bit Holding capacitor is disconnected from analog input (typically 100 ns) TAD9 TAD10 TCY - TAD ADRESH:ADRESL is loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. Conversion starts b0 b9 b6 b5 b4 b3 b2 b1 b8 b7 On the following cycle: TAD1 Discharge 1 2 3 4 5 6 7 8 11 Set GO/DONE bit (Holding capacitor is disconnected) 9 10 Conversion starts 1 2 3 4 (Holding capacitor continues acquiring input) TACQT Cycles TAD Cycles Automatic Acquisition Time b0 b9 b6 b5 b4 b3 b2 b1 b8 b7 ADRESH:ADRESL is loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. On the following cycle: TAD1 Discharge |
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