PIC18F44J10-ESLASHML datasheet(218/358 Pages) MICROCHIP

218 / 358 page

PIC18F45J10 FAMILY

DS39682C-page 216

Preliminary

17.4

Operation in Power-Managed

Modes

The selection of the automatic acquisition time and A/D

conversion clock is determined in part by the clock

source and frequency while in a power-managed mode.

If the A/D is expected to operate while the device is in

a power-managed mode, the ACQT2:ACQT0 and

ADCS2:ADCS0 bits in ADCON2 should be updated in

accordance with the clock source to be used in that

mode. After entering the mode, an A/D acquisition or

conversion may be started. Once started, the device

should continue to be clocked by the same clock

source until the conversion has been completed.

If desired, the device may be placed into the

corresponding Idle mode during the conversion. If the

device clock frequency is less than 1 MHz, the A/D RC

clock source should be selected.

Operation in the Sleep mode requires the A/D FRC

clock to be selected. If bits ACQT2:ACQT0 are set to

‘000’ and a conversion is started, the conversion will be

delayed one instruction cycle to allow execution of the

SLEEP

instruction and entry to Sleep mode. The IDLEN

bit (OSCCON<7>) must have already been cleared

prior to starting the conversion.

17.5

A/D Converter Calibration

The A/D converter in the PIC18F45J10 family of

devices includes a self-calibration feature which com-

pensates for any offset generated within the module.

The calibration process is automated and is initiated by

setting the ADCAL bit (ADCON0<7>). The next time

the GO/DONE bit is set, the module will perform a

“dummy” conversion (that is, with reading none of the

input channels) and store the resulting value internally

to compensate for offset. Thus, subsequent offsets will

be compensated.

The calibration process assumes that the device is in a

relatively steady-state operating condition. If A/D

calibration is used, it should be performed after each

device Reset, or if there are other major changes in

operating conditions.

17.6

Configuring Analog Port Pins

The ADCON1, TRISA, TRISB and TRISE registers all

configure the A/D port pins. The port pins needed as

analog inputs must have their corresponding TRIS bits

set (input). If the TRIS bit is cleared (output), the digital

output level (VOH or VOL) will be converted.

The A/D operation is independent of the state of the

CHS3:CHS0 bits and the TRIS bits.

Note 1: When reading the Port register, all pins

configured as analog input channels will

read as cleared (a low level). Pins con-

figured as digital inputs will convert as

analog inputs. Analog levels on a digitally

configured

input

will

accurately

converted.

2: Analog levels on any pin defined as a dig-

ital input may cause the digital input buffer

to consume current out of the device’s

specification limits.

3: The

PBADEN

bit

Configuration

reset as analog or digital pins by control-

ling how the PCFG0 bits in ADCON1 are

reset.

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