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PIC18F44J10-E/ML 데이터시트(PDF) 222 Page - Microchip Technology

부품명 PIC18F44J10-E/ML
상세설명  28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology
PDF  358 Pages
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제조업체  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

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PIC18F45J10 FAMILY
DS39682C-page 220
Preliminary
© 2007 Microchip Technology Inc.
18.1
Comparator Configuration
There are eight modes of operation for the compara-
tors, shown in Figure 18-1. Bits CM2:CM0 of the
CMCON register are used to select these modes. The
TRISA register controls the data direction of the com-
parator pins for each mode. If the Comparator mode is
changed, the comparator output level may not be valid
for the specified mode change delay shown in
Section 23.0 “Electrical Characteristics”.
FIGURE 18-1:
COMPARATOR I/O OPERATING MODES
Note:
Comparator interrupts should be disabled
during
a
Comparator
mode
change;
otherwise, a false interrupt may occur.
C1
RA0/AN0
VIN-
VIN+
RA3/AN3/
Off (Read as ‘0’)
Comparators Reset
A
A
CM2:CM0 = 000
C2
RA1/AN1
VIN-
VIN+
RA2/AN2/
Off (Read as ‘0’)
A
A
C1
VIN-
VIN+
C1OUT
Two Independent Comparators
A
A
CM2:CM0 = 010
C2
VIN-
VIN+
C2OUT
A
A
C1
VIN-
VIN+
C1OUT
Two Common Reference Comparators
A
A
CM2:CM0 = 100
C2
VIN-
VIN+
C2OUT
A
D
C2
VIN-
VIN+
Off (Read as ‘0’)
One Independent Comparator with Output
D
D
CM2:CM0 = 001
C1
VIN-
VIN+
C1OUT
A
A
C1
VIN-
VIN+
Off (Read as ‘0’)
Comparators Off (POR Default Value)
D
D
CM2:CM0 = 111
C2
VIN-
VIN+
Off (Read as ‘0’)
D
D
C1
VIN-
VIN+
C1OUT
Four Inputs Multiplexed to Two Comparators
A
A
CM2:CM0 = 110
C2
VIN-
VIN+
C2OUT
A
A
From VREF Module
CIS = 0
CIS = 1
CIS = 0
CIS = 1
C1
VIN-
VIN+
C1OUT
Two Common Reference Comparators with Outputs
A
A
CM2:CM0 = 101
C2
VIN-
VIN+
C2OUT
A
D
A = Analog Input, port reads zeros always
D = Digital Input
CIS (CMCON<3>) is the Comparator Input Switch
CVREF
C1
VIN-
VIN+
C1OUT
Two Independent Comparators with Outputs
A
A
CM2:CM0 = 011
C2
VIN-
VIN+
C2OUT
A
A
RA5/AN4/SS1/C2OUT*
RB5/KBI1/T0CKI/C1OUT*
VREF+
VREF-/CVREF
RA0/AN0
RA3/AN3/
RA1/AN1
RA2/AN2/
VREF+
VREF-/CVREF
RA0/AN0
RA3/AN3/
RA1/AN1
RA2/AN2/
VREF+
VREF-/CVREF
RA0/AN0
RA3/AN3/
RA1/AN1
RA2/AN2/
VREF+
VREF-/CVREF/
RA0/AN0
RA3/AN3/
RA1/AN1
RA2/AN2/
VREF+
VREF-/CVREF/
RA0/AN0
RA3/AN3/
RA1/AN1
RA2/AN2/
VREF+
VREF-/CVREF
RA0/AN0
RA3/AN3/
VREF+
RA1/AN1
RA2/AN2/
VREF-/CVREF
RB5/KBI1/
RA5/AN4/SS1/C2OUT*
RA0/AN0
RA3/AN3/
VREF+
RA1/AN1
RA2/AN2/
VREF-/CVREF
RB5/KBI1/
* Setting the TRISA<5> bit will disable the comparator outputs by configuring the pins as inputs.
T0CKI/C1OUT*
T0CKI/C1OUT*



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