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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PIC18F44J10-E/ML 데이터시트(PDF) 225 Page - Microchip Technology |
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PIC18F44J10-E/ML 데이터시트(HTML) 225 Page - Microchip Technology |
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225 / 358 page  © 2007 Microchip Technology Inc. Preliminary DS39682C-page 223 PIC18F45J10 FAMILY 18.9 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 18-4. Since the analog pins are connected to a digital output, they have reverse biased diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up condition may occur. A maximum source impedance of 10 k Ω is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current. FIGURE 18-4: COMPARATOR ANALOG INPUT MODEL TABLE 18-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE VA RS < 10k AIN CPIN 5 pF VDD VT = 0.6V VT = 0.6V RIC ILEAKAGE ±500 nA VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage Comparator Input Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 45 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 45 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 46 PIR2 OSCFIF CMIF — — BCL1IF — — CCP2IF 45 PIE2 OSCFIE CMIE — — BCL1IE — — CCP2IE 45 IPR2 OSCFIP CMIP — — BCL1IP — — CCP2IP 45 PORTA — —RA5 — RA3 RA2 RA1 RA0 46 LATA — — PORTA Data Latch Register (Read and Write to Data Latch) 46 TRISA — — TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0 46 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module. |
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