PIC18F4685-ISLASHSP datasheet(126/484 Pages) MICROCHIP

126 / 484 page

PIC18F2682/2685/4682/4685

DS39761B-page 124

Preliminary

9.4

IPR Registers

The IPR registers contain the individual priority bits for

the peripheral interrupts. Due to the number of

peripheral interrupt sources, there are two Peripheral

Interrupt Priority registers (IPR1, IPR2). Using the

priority bits requires that the Interrupt Priority Enable

(IPEN) bit be set.

IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1

R/W-1

PSPIP(1)

ADIP

RCIP

TXIP

SSPIP

CCP1IP

TMR2IP

TMR1IP

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1)

= High priority

= Low priority

bit 6

ADIP: A/D Converter Interrupt Priority bit

= High priority

= Low priority

bit 5

RCIP: EUSART Receive Interrupt Priority bit

= High priority

= Low priority

bit 4

TXIP: EUSART Transmit Interrupt Priority bit

= High priority

= Low priority

bit 3

SSPIP: Master Synchronous Serial Port Interrupt Priority bit

= High priority

= Low priority

bit 2

CCP1IP: CCP1 Interrupt Priority bit

= High priority

= Low priority

bit 1

TMR2IP: TMR2 to PR2 Match Interrupt Priority bit

= High priority

= Low priority

bit 0

TMR1IP: TMR1 Overflow Interrupt Priority bit

= High priority

= Low priority

Note 1:

This bit is reserved on PIC18F2682/2685 devices; always maintain this bit clear.

PIC18F4685-I/SP 데이터시트(PDF) 126 Page - Microchip Technology

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