CS4525 datasheet(48/98 Pages) CIRRUS

48 / 98 page

DS726PP1

CS4525

6.1.8.3

Recommended PWM_SIG Power-Up Sequence for Headphone & Line-

Out

1. Set the PDnAll bit in the Power Ctrl register to stop the PWM modulators if it is not already set.

2. Configure the PWM_SIG outputs as desired via the PWMDSel[1:0] bits in the Output Cfg register.

3. Clear the PDnAll bit in the Power Ctrl register to start the PWM modulators.

4. Wait 500 ms to allow the internal sample rate converters to achieve lock.

5. Set the HiZPSig bit in the EQ Config register to activate the PWM_SIG outputs.

6.1.8.4

Recommended PWM_SIG Power-Down Sequence for Headphone &

Line-Out

1. Mute the PWM_SIG outputs to a 50% duty-cycle by either setting Master Volume to 1111 1111h

(Master Mute) or through use of the HP_DETECT/MUTE input pin as described in the Headphone

Detection & Hardware Mute Input section on page 51.

2. Clear the HiZPSig bit in the EQ Config register to put the PWM_SIG output drivers in a high-imped-

ance state.

3. Power down the remainder of the system (if applicable).

Referenced Control

PDnAll ................................. “Power Down (PDnAll)” on page 89

HiZPSig ............................... “Hi-Z PWM_SIG Outputs (HiZPSig)” on page 79

PWMDSel[1:0]..................... “PWM Signals Output Data Select (PWMDSel[1:0])” on page 73

Master Volume .................... “Master Volume Control (MVol[7:0])” on page 82

CS4525 데이터시트(PDF) 48 Page - Cirrus Logic