CS4525 datasheet(91/98 Pages) CIRRUS

91 / 98 page

DS726PP1

CS4525

cleared, the SRCLock condition is masked, meaning that its occurrence will not affect the INT pin. How-

ever, the SRCLock and SRCLockSt bits will continue to reflect the lock status of the SRC.

9.20.6 Mask for ADC Overflow (ADCOvflM)

Default = 0

Function:

This bit serves as a mask for the ADC overflow interrupt source. If this bit is set, the ADCOvfl interrupt is

unmasked, meaning that if the ADCOvfl bit is set, the INT pin will go active. If the ADCOvflM bit is cleared,

the ADCOvfl condition is masked, meaning that its occurrence will not affect the INT pin. However, the

ADCOvfl and ADCOvflSt bits will continue to reflect the overflow state of the ADC.

9.20.7 Mask for Channel X and Sub Overflow (ChOvflM)

Default = 0

Function:

This bit serves as a mask for the channel 1, 2, and Sub overflow interrupt source. If this bit is set, the ChO-

vfl interrupt is unmasked, meaning that if the ChOvfl bit is set, the INT pin will go active. If the ChOvflM bit

is cleared, the ChOvfl condition is masked, meaning that its occurrence will not affect the INT pin. How-

ever, the ChOvfl, ChXOvflSt, and SubOvflSt bits will continue to reflect the overflow state of the individual

channels.

9.20.8 Mask for Amplifier Error (AmpErrM)

Default = 0

Function:

This bit serves as a mask for the amplifier error interrupt sources. If this bit is set, the AmpErr interrupt is

unmasked, meaning that if the AmpErr bit is set, the INT pin will go active. If the AmpErrM bit is cleared,

the AmpErr condition is masked, meaning that its occurrence will not affect the INT pin. However, the Am-

pErr and the amplifier error bits in the amplifier error status register will continue to reflect the status of the

amplifier error conditions.

SRCLockM Setting

SRCLock INT Pin Mask State

0 ..........................................SRCLock condition masked.

1 ..........................................SRCLock condition un-masked.

ADCOvflM Setting

ADCOvfl INT Pin Mask State

0 ..........................................ADCOvfl condition masked.

1 ..........................................ADCOvfl condition un-masked.

ChOvflM Setting

ChOvfl INT Pin Mask State

0 ..........................................ChOvfl condition masked.

1 ..........................................ChOvfl condition un-masked.

AmpErrM Setting

AmpErr INT Pin Mask State

0 ..........................................AmpErr condition masked.

1 ..........................................AmpErr condition un-masked.

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