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PWD5T60 데이터시트(PDF) 12 Page - STMicroelectronics

부품명 PWD5T60
상세설명  Compact high-voltage three-phase power stage with integrated gate driver
PDF  27 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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PWD5T60 데이터시트(HTML) 12 Page - STMicroelectronics

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6
Functional description
6.1
Inputs and outputs
The device is controlled through the following logic inputs:
•
EN: enable input, active high;
•
LIN: low-side driver inputs, active high;
•
HIN: high-side driver inputs, active high.
Table 9. Inputs truth table (applicable when the device is not in UVLO or SmartSD protection)
Input pins
Output pins
EN
LIN
HIN
LVG
HVG
L
X
X
OFF
OFF
H
L
L
OFF
OFF
H
H
L
ON
OFF
H
L
H
OFF
ON
Interlocking
H
H
H
OFF
OFF
Note:
X : Do not care.
The FAULT and OD pins are open-drain outputs.
The FAULT signal is set low in case VCC UVLO is detected, or in case the SmartShutDown comparator triggers
an event. It is only used to signal a UVLO or SmartSD activation to external circuits, and its state does not affect
the behavior of other functions or circuits inside the driver.
The OD behavior is explained in Section 6.5.
6.2
Deadtime
The deadtime feature, in companion with the interlocking feature, guarantees that driver outputs of the same
channel are not high simultaneously and at least a DT time passes between the turn-off of one driver's output and
the turn-on of the companion output of the same channel. If a deadtime longer than the internal DT is applied to
the LIN and HIN inputs by the external controller, the internal DT is ignored and the outputs follow the deadtime
determined by the inputs.
PWD5T60
Functional description
DS14558 - Rev 2
page 12/27



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