Figure 14. Smart shutdown timing waveforms

SMART SHUTDOWN CIRCUIT

LVG/HVG

OD gate

(internal)

CIN

Fast shut down

the driver outputs are switched off

disable time

OD

FAULT

VREF

tFCIN

tFCIN

tCINoff

VSSDh

VSSDl

VOD

t1

t2

OD

COD

SMART

SD

LOGIC

RON_OD

IOD

5 V

VCC

OD

COD

SMART

SD

LOGIC

RON_OD

IOD

5 V

ROD_ext

external pull-up

2

1

immediately after the comparator triggering

6.6

Overtemperature protection

The device integrates an overtemperature protection, which turns and keeps all MOSFETs off when TJ exceeds

TTSD.

Overtemperature protection is signaled externally setting the FAULT pin low.

Once TJ falls below (TTSD - THYS ) the FAULT pin is released and the MOSFETs are set according to the logic

input values.

PWD5T60

Functional description

DS14558 - Rev 2

page 16/27