CS42448 datasheet(46/64 Pages) CIRRUS

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DS648F2

CS42448

6.6.2

ADC3 High Pass Filter Freeze (ADC3_HPF FREEZE)

Default = 0

Function:

When this bit is set, the internal high-pass filter will be disabled for ADC3.The current DC offset value will

be frozen and continue to be subtracted from the conversion result. See “ADC Digital Filter Characteris-

tics” on page 13.

6.6.3

DAC De-Emphasis Control (DAC_DEM)

Default = 0

0 - No De-Emphasis

1 - De-Emphasis Enabled (Auto-Detect Fs)

Function:

Enables the digital filter to maintain the standard 15

μs/50μs digital de-emphasis filter response at the

auto-detected sample rate of either 32, 44.1, or 48 kHz. De-emphasis will not be enabled, regardless of

this register setting, at any other sample rate.

6.6.4

ADC1 Single-Ended Mode (ADC1 SINGLE)

Default = 0

0 - Disabled; Differential input to ADC1

1 - Enabled; Single-Ended input to ADC1

Function:

When enabled, this bit allows the user to apply a single-ended input to the positive terminal of ADC1. A

+6 dB digital gain is automatically applied to the serial audio data of ADC1. The negative leg must be driv-

en to the common mode of the ADC. See Figure 27 on page 53 for a graphical description.

6.6.5

ADC2 Single-Ended Mode (ADC2 SINGLE)

Default = 0

0 - Disabled; Differential input to ADC2

1 - Enabled; Single-Ended input to ADC2

Function:

When enabled, this bit allows the user to apply a single-ended input to the positive terminal of ADC2. A

+6 dB digital gain is automatically applied to the serial audio data of ADC2. The negative leg must be driv-

en to the common mode of the ADC. See Figure 27 on page 53 for a graphical description.

CS42448 데이터시트(PDF) 46 Page - Cirrus Logic