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CS42448 데이터시트(PDF) 34 Page - Cirrus Logic |
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CS42448 데이터시트(HTML) 34 Page - Cirrus Logic |
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34 / 64 page ![]() 34 DS648F2 CS42448 4.5.7 I/O Channel Allocation 4.6 AUX Port Digital Interface Formats These serial data lines are used when supporting the TDM Mode of operation with an external ADC or S/PDIF receiver attached. The AUX serial port operates only as a clock master. The AUX_SCLK will operate at 64xFs, where Fs is equal to the ADC sample rate (ADC_LRCK). If the AUX_SDIN signal is not being used, it should be tied to AGND via a pull-down resistor. The AUX port will operate in either the Left-Justified or I²S digital interface format with bit depths ranging from 16 to 24 bits. Settings for the AUX port are made through the register “Interface Formats (Address 04h)” on page 44. 4.6.1 I²S 4.6.2 Left-Justified Digital Input/Output Interface Format Analog Output/Input Channel Allocation from/to Digital I/O DAC_SDIN1 I²S, LJ, RJ OLM TDM AOUT 1,2 AOUT 1,2,3,4,5,6 AOUT 1,2,3,4,5,6,7,8 DAC_SDIN2 I²S, LJ, RJ OLM TDM AOUT 3,4 Not Used Not Used DAC_SDIN3 I²S, LJ, RJ OLM TDM AOUT 5,6 Not Used Not Used DAC_SDIN4 I²S, LJ, RJ OLM TDM AOUT 7,8 AOUT 7,8 Not Used ADC_SDOUT1 I²S, LJ, RJ OLM TDM AIN 1,2 AIN 1,2,3,4,5,6 AIN 1,2,3,4,5,6; (2 additional channels from AUX_SDIN) ADC_SDOUT2 I²S, LJ, RJ OLM TDM AIN 3,4 Not Used Not Used ADC_SDOUT3 I²S, LJ, RJ OLM TDM AIN 5,6 Not Used Not Used Table 9. Serial Audio Interface Channel Allocations AUX_LRCK AUX_SCLK MS B LS B MS B LS B AUX1 L eft C h an nel R ig ht C h an nel AUX_SDIN AUX2 MSB Figure 21. AUX I²S Format |
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