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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ICS1893CF 데이터시트(PDF) 112 Page - Integrated Circuit Systems |
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ICS1893CF 데이터시트(HTML) 112 Page - Integrated Circuit Systems |
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112 / 126 page  ICS1893CF, Rev. F, 03/01/07 Mar. 2007 112 Chapter 9 DC and AC Operating Conditions ICS1893CF Data Sheet - Release Copyright © 2007, Integrated Device Technology, Inc. All rights reserved. 9.5.10 100M / MII Media Independent Interface: Transmit Latency Table 9-17 lists the significant time periods for the MII / 100 Stream Interface transmit latency. The time periods consist of timings of signals on the following pins: • TXEN • TXCLK • TXD (that is, TXD[3:0]) • TP_TX (that is, TP_TXP and TP_TXN) Figure 9-11 shows the timing diagram for the time periods. † The IEEE maximum is 18 bit times. Figure 9-11. MII / 100M Stream Interface Transmit Latency Timing Diagram Table 9-17. MII / 100M Stream Interface Transmit Latency Time Period Parameter Conditions Min. Typ. Max. Units t1 TXEN Sampled to MDI Output of First Bit of /J/ † MII mode – 2.8 3 Bit times TXEN TXCLK TXD TP_TX† † Shown unscrambled. t1 Preamble /K/ Preamble /J/ |
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