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PM5366-PI 데이터시트(PDF) 22 Page - PMC-Sierra, Inc

부품명 PM5366-PI
상세설명  HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER AND M13 MULTIPLEXER
PDF  267 Pages
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제조업체  PMC [PMC-Sierra, Inc]
홈페이지  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

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PRELIMINARY
PM5366 TEMAP-84
DATASHEET
PMC-2010672
ISSUE 1
HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER
AND M13 MULTIPLEXER
PROPRIETARY AND CONFIDENTIAL
10
DS2 Framer Section:
• Frames to a DS2 (ANSI T1.107 section 8) signal with a maximum average
reframe time of less than 7 ms (as required by TR-TSY-000009 Section 4.1.2
and TR-TSY-000191 Section 5.2).
• Detects the DS2 alarm indication signal (AIS) in 9.9 ms in the presence of a 10-3
bit error rate.
• Extracts the DS2 X-bit remote alarm indication (RAI) bit and indicates far end
receive failure (FERF). The far end receive failure status only changes when the
associated bit has been in the same state for two consecutive frames. The
status is buffered for six M-frames, ensuring a better than 99.9% chance of
freezing the correct status for the duration of the out of frame occurrence.
• Accumulates up to 255 DS2 M-bit or F-bit error events per second.
DS2 Transmitter Section:
• Generates the required X, F, and M bits into the transmitted DS2 bit stream.
Allows inversion of inserted F or M bits for diagnostic purposes.
• Provides for transmission of far end receive failure (FERF) and alarm indication
signal (AIS) under microprocessor control.
• Provides optional automatic insertion of far end receive failure (FERF) on
detection of out of frame (OOF), alarm indication signal (AIS) or red alarm
condition.
M12 Multiplexer Section:
• Multiplexes four DS1 or three 2048 kbit/s (according to ITU-T Rec. G.747) bit
streams into a single M12 format DS2 bit stream.
• Performs required bit stuffing including generation and interpretation of C-bits.
• Includes required FIFO buffers for rate adaptation in the multiplex path.
• Performs required inversion of second and fourth multiplexed DS1 streams as
required by ANSI T1.107 Section 7.2.
• Allows insertion and detection of per DS1 payload loopback requests encoded in
the C-bits to be activated under microprocessor control.



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