PM5366-PI datasheet(46/267 Pages) PMC

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PRELIMINARY

PM5366 TEMAP-84

DATASHEET

PMC-2010672

ISSUE 1

HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER

AND M13 MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL

Pin Name

Type

No.

Function

Flexible Bandwidth Ports

Port #1 is associated with SBI SPE #1. Port #2 is associated with SBI SPE #2.

Port #3 is associated with SBI SPE #3.

IFBWCLK[3]

IFBWCLK[2]

IFBWCLK[1]

Input

N22

K19

H19

The Ingress Flexible Bandwidth Clocks

(IFBWCLK[3:1]). The IFBWCLK[3:1] clocks provide

the timing for an arbitrary bandwidth payload to be

inserted into the System Drop Bus (SDDATA[7:0]).

Each clock is associated with one SPE and is only

used when the associated SPE is configured to carry a

fractional payload by the OPMODE_SPEx[2:0] bits of

the SPE Configuration registers.

IFBWCLK[3:1] may have a maximum frequency of

51.84 MHz and may be gapped if required.

Each IFBWCLK samples the associated

IFBWDAT[3:1] and IFBWEN[3:1] inputs on the rising

edge.

IFBWDAT[3]

IFBWDAT[2]

IFBWDAT[1]

Input

N20

L20

J20

The Ingress Flexible Bandwidth Data

(IFBWDAT[3:1]). These inputs present bit serial data

for insertion into the System Drop Bus (SDDATA[7:0]).

Only bits for which the associated IFBWEN input is

sampled high are accepted. Each data input is

associated with one SPE and is only used when the

associated SPE is configured to carry a fractional

payload by the OPMODE_SPEx[2:0] bits of the SPE

Configuration registers.

IFBWDAT[3:1] are sampled on the rising edge of the

associated IFBWCLK input.

IFBWEN[3]

IFBWEN[2]

IFBWEN[1]

Input

P19

L22

J21

The Ingress Flexible Bandwidth Enables

(IFBWEN[3:1]). A logic high on any of these inputs

indicates a valid bit on the associated IFBWDAT input.

The IFBWEN[3:1] inputs are constrained such that the

maximum data rate of each of IFBWDAT[3:1] is less

than 49.72 Mbit/s.

IFBWEN[3:1] are sampled on the rising edge of the

associated IFBWCLK input.

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