PM5366-PI datasheet(172/267 Pages) PMC

172 / 267 page

PRELIMINARY

PM5366 TEMAP-84

DATASHEET

PMC-2010672

ISSUE 1

HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER

AND M13 MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL

160

The bit error rate for T1 ESF can be calculated from the one-second PMON

CRCE count by the following equation:

Bit Error Rate = 1 - 10

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æ −

193

8000

log

BEE

Figure 16

- CRCE Count vs. BER (T1 ESF mode)

1.00E-07

1.00E-06

1.00E-05

1.00E-04

1.00E-03

1.00E-02

100

150

200

250

300

350

CRCE

For T1 SF format, the CRCE and FER counts are identical, but the FER counter

is smaller and should be ignored.

Figure 17

- CRCE Count vs. BER (T1 SF mode)

200

400

600

800

1000

1200

Bit Error Event Count Per Second

Average Count Over

Many 1 Second Intervals

12.6 Using the Internal DS3 or E3 HDLC Transmitter

It is important to note that access rate to the TDPR registers is limited by the rate

of the internal DS3/E3 clock. Consecutive accesses to the TDPR Configuration,

TDPR Interrupt Status/UDR Clear, and TDPR Transmit Data register should be

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