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PM5366-PI 데이터시트(PDF) 179 Page - PMC-Sierra, Inc |
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PM5366-PI 데이터시트(HTML) 179 Page - PMC-Sierra, Inc |
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179 / 267 page ![]() PRELIMINARY PM5366 TEMAP-84 DATASHEET PMC-2010672 ISSUE 1 HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER AND M13 MULTIPLEXER PROPRIETARY AND CONFIDENTIAL 167 Figure 18 - Typical Data Frame 87 65 43 2 1 01 11 11 1 0 FLAG Address (high) (low) CONTROL Frame Check Sequence 01 11 11 1 0 FLAG data bytes received and transferred to the FIFO Buffer BIT: Bit 1 is the first serial bit to be received. When enabled, the primary, secondary and universal addresses are compared with the high order packet address to determine a match. Figure 19 - Example Multi-Packet Operational Sequence DATA INT FE LA 12 3 4 5 6 7 F F F FA D D D DD D D D D DDDD D F F F FD D D DF F F - flag sequence (01111110) A - abort sequence (01111111) D - packet data bytes INT - active high interrupt output FE - internal FIFO empty status LA - state of the LINK ACTIVE software flag Figure 19 shows the timing of interrupts, the state of the FIFO, and the state of the Data Link relative the input data sequence. The cause of each interrupt and |
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