M69KB128AA85CW8 datasheet(7/68 Pages) STMICROELECTRONICS

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M69KB128AA

1 Summary description

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Summary description

The M69KB128AA is a 128 Mbit (134,217,728 bit) PSRAM, organized as 8,388,608 Words by

16 bits. It uses a high-speed CMOS DRAM technology implemented using a one transistor-per-

cell topology that achieves bigger array sizes. It provides a high-density solution for low-power

handheld applications.

The M69KB128AA is supplied by a 1.7 to 1.95V supply voltage range.

The PSRAM interface supports various operating modes: Asynchronous Random Read and

Write, Asynchronous Page Read and Synchronous mode that increases read/write speed.

In Asynchronous Random Read mode, the M69KB128AA is compatible with low power

SRAMs. In Asynchronous Page mode the device has much shorter access times within the

page that make it is compatible with the industry standard PSRAMs.

Two types of Synchronous modes are available:

●

Flash-NOR: the device operates in Synchronous mode for read operations and

Asynchronous mode for write operations.

●

Full Synchronous: the device supports Synchronous transfers for both read and write

operations.

The M69KB128AA features three configuration registers:

●

Two user-programmable registers used to define the device operation: the Bus

Configuration Register (BCR) and the Refresh Configuration Register (RCR).

●

A read-only Device ID Register (DIDR) containing device identification.

The Bus Configuration Register (BCR) indicates how the device interacts with the system

memory bus. The Refresh Configuration Register (RCR) is used to control how the memory

array refresh is performed. At Power-Up, these registers are automatically loaded with default

settings and can be updated any time during normal operation.

PSRAMs are based on the DRAM technology, but have a transparent internal self-refresh

mechanism that requires no additional support from the system memory microcontroller.

To minimize the value of the Standby current during self-refresh operations, the M69KB128AA

includes two system-accessible mechanisms configured via the Refresh Configuration Register

(RCR):

●

The Partial Array Self Refresh (PASR) performs a limited refresh of the part of the PSRAM

array that contains essential data.

●

The Deep Power-Down (DPD) mode completely halts the refresh operation. It is used

when no essential data is being held in the device.

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