전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

M69KB128AA85CW8 데이터시트(PDF) 17 Page - STMicroelectronics

부품명 M69KB128AA85CW8
상세설명  128 Mbit (8Mb x16) 1.8V Supply, Burst PSRAM
PDF  68 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M69KB128AA85CW8 데이터시트(HTML) 17 Page - STMicroelectronics

Back Button M69KB128AA85CW8 Datasheet HTML 13Page - STMicroelectronics M69KB128AA85CW8 Datasheet HTML 14Page - STMicroelectronics M69KB128AA85CW8 Datasheet HTML 15Page - STMicroelectronics M69KB128AA85CW8 Datasheet HTML 16Page - STMicroelectronics M69KB128AA85CW8 Datasheet HTML 17Page - STMicroelectronics M69KB128AA85CW8 Datasheet HTML 18Page - STMicroelectronics M69KB128AA85CW8 Datasheet HTML 19Page - STMicroelectronics M69KB128AA85CW8 Datasheet HTML 20Page - STMicroelectronics M69KB128AA85CW8 Datasheet HTML 21Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 17 / 68 page
background image
M69KB128AA
5 Standard asynchronous operating modes
17/68
Table 3.
Standard Asynchronous Operating Modes
Asynchronous
Modes(1)
1.
The Clock signal, K, must remain Low in asynchronous operating mode.
Power
L
E
W
G
UB
LB
WAIT
CR
A19 A18
A0-A17
A20-A22
DQ0-
DQ7
DQ8-
DQ15
Word Read
Active
(ICC)
VIL
VIL
VIH
VIL VIL VIL
Low-
Z
VIL
Valid
Output
Valid
Output
Valid
Lower Byte
Read
VIL VIH VIL
VIL
Valid
Output
Valid
High-Z
Upper Byte
Read
VIL VIL VIH
VIL
Valid
High-Z
Output
Valid
Word Write
VIL
X
VIL VIL
VIL
Valid
Input
Valid
Input
Valid
Lower Byte
Write
X
VIH VIL
VIL
Valid
Input
Valid
Invalid
Upper Byte
Write
X
VIL VIH
VIL
Valid
Invalid
Input
Valid
Read
Configuration
Register
(CR Controlled
Method)
VIH VIL VIL VIL
VIH
00(RCR)
10(BCR)
X1(DIDR)
(2)
2.
A18 and A19 are used to select the BCR, RCR or DIDR registers.
X
BCR/
RCR/DIDR
Content
Program
Configuration
Register (CR
Controlled)(3)
3.
BCR and RCR only.
VIH
XX
X
00(RCR)
10(BCR)
(2)
BCR/
RCR
Data
High-Z
No Operation
Active
(ICC)
X
XX
X
X
VIL
XX
X
X
Deep
Power-Down(4)
4.
Bit 4 of the Refresh Configuration Register must be set to ‘0’, bit 4 (BCR4) of the Bus Configuration Register must be set to
‘0’, and E has to be maintained High, VIH, during Deep Power-Down mode.
Deep
Power-
Down
(ICCPD)
VIH
XX
X
X
High-
Z
X
X
X
X
High-Z
Standby
Standby
(IPASR)
VIH
XX
X
X
VIL
X
X
X
High-Z



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com