R2023K datasheet(37/50 Pages) RICOH

37 / 50 page

R2023K/T

32768Hz Oscillation

Power-on reset flag

(PON)

Oscillation halt

sensing flag (XST)

Threshold voltage (2.1V or 1.35V)

VDD

VDD supply voltage

monitor flag (VDET)

Internal initialization

period (1 to 2 sec.)

VDET

←0

XST

←1

PON

←0

VDET

←0

XST

←1

PON

←1

VDET

←0

XST

←1

PON

←0

Internal initialization

period (1 to 2 sec.)

When the PON bit is set to 1 in the control register 2, the DEV, F6 to F0, WALE, DALE, 12 /24, CLEN2 , TEST,

CT2, CT1, CT0, VDSL, VDET, CLEN1 , CTFG, WAFG, and DAFG bits are reset to 0 in the oscillation adjustment

The PON bit is also set to 1 at power-on from 0 volts.

< Considerations in Using Oscillation Halt Sensing Circuit >

Be sure to prevent the oscillation halt sensing circuit from malfunctioning by preventing the following:

1) Instantaneous power-down on the VDD

2) Condensation on the quartz crystal unit

3) On-board noise to the quartz crystal unit

4) Applying to individual pins voltage exceeding their respective maximum ratings

In particular, note that the XST bit may fail to be set to 0 in the presence of any applied supply voltage as

illustrated below in such events as backup battery installation. Further, give special considerations to prevent

excessive chattering in the oscillation halt sensing circuit.

VDD

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