405EX datasheet(53/67 Pages) AMCC

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PPC405EX – PowerPC 405EX Embedded Processor

Revision 1.09 - August 21, 2007

AMCC Proprietary

Preliminary Data Sheet

Table 16. Peripheral Interface I/O Clock Timings

Clock

Min

Max

Units

GMCTxClk frequency

125

MHz

GMCTxClk high time

45% of nominal

–

GMCTxClk low time

55% of nominal

–

GMCRxClk frequency

125

MHz

GMCRxClk high time

45% of nominal

–

GMCRxClk low time

55% of nominal

–

GMCGTxClk

125

MHz

GMCMDClk

2.5

MHz

GMCRefClk

125

MHz

GMCRefClk edge stability (phase jitter, cycle-to-cycle)

± 0.1

GMCRefClk rise time

0.4

GMCRefClk high time

40% of nominal

–

GMCRefClk low time

60% of nominal

–

GMCnRxClk

125

MHz

GMCnTxClk

125

MHz

UARTSerClk

1000/(2TOPB1 + 2ns)

MHz

TmrClk

100

MHz

PerClk

100

MHz

TCK

MHz

USB2Clk (60MHz ± 0.05%)

57.97

60.03

MHz

PCIEnClkC, T (Differential clock input)

100

250

MHz

Notes:

1. TOPB is the period in ns of the OPB clock. The internal OPB clock runs at an integral divisor ratio of the frequency of the PLB clock. The

maximum OPB clock frequency is 100MHz.

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