405EX datasheet(9/67 Pages) AMCC

9 / 67 page

PPC405EX – PowerPC 405EX Embedded Processor

Revision 1.09 - August 21, 2007

AMCC Proprietary

Preliminary Data Sheet

OPB

The OPB provides 32-bit address and data interfaces, and operates up to 100MHz. There are bridges between the

OPB and the PLB.

Features include:

• Pipelined read support

• Dynamic bus sizing

• Single-cycle data transfer between masters and slaves

DCR Bus

The daisy-chained DCR bus provides a path for passing status and control information between the processor core

and the other on-chip cores. All DCRs are 32 bits in width with 10-bit addressing.

External Bus Controller

The external bus controller (EBC and EBM ) transfers data between the PLB and external memory or peripheral

devices attached to the external peripheral bus. The EBC provides direct attachment of memory devices such as

ROM and SRAM, DMA device paced memory devices, and DMA peripheral devices.

Features include:

• From 60MHz to 100 MHz speed

• Data bus is 8, 16, or 32 bits with a 27-bit address bus

• Up to four chip selects

• Arbitration and multi-master supported

• Flash ROM interface

• Boot from EBC (including NAND Flash interface) support

• Direct support for 8-,16-, or 32-bit SRAM and external peripherals

• External bus master support

NAND Flash Controller

The NAND Flash controller (NDFC) provides a simple interface between the External Bus Controller (EBC) and a

variety of NAND Flash-based storage devices.

Features include:

• Attachment as internal EBC slave device

• Eight- and 16-bit NAND Flash interface

• Up to four banks of NAND Flash supported

• Device sizes of 4MB to 256MB (32Mb to 2Gb) supported

• 512B + 16B or 2kB + 64B device page sizes supported

• ECC generation - hamming code, single-bit correction, double-bit detection (SEC/DED)

• Eight-bit command write, address write, and data read/write

• Interrupt on device ready (after long page write or block erase operations)

• Boot from NAND

– Executes up to 4KB of boot code out of first block

– Automatic page read accesses performed based on device configuration and read address

DMA Controller

The Direct Memory Access (DMA) controller is a Processor Local Bus (PLB) master that enables faster data

transfer between memory and peripherals than is possible under program control. The 4-channel DMA controller

handles data transfers between memory and peripherals and from memory-to-memory. Each channel has an

independent set of registers needed for data transfer: a control register, a source address register, a destination

address register, and a transfer count register.

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