405EX datasheet(59/67 Pages) AMCC

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PPC405EX – PowerPC 405EX Embedded Processor

Revision 1.09 - August 21, 2007

AMCC Proprietary

Preliminary Data Sheet

DDR SDRAM Write Operation

The rising edge of MemClkOut aligns with the first rising edge of the DQS signal on writes. The following data is

generated by means of simulation and includes logic, driver, package RLC, and lengths. Values are calculated

over best case and worst case processes with speed, junction temperature, and voltage as follows:

Note: In the following tables and timing diagrams, minimum values are measured under best case conditions and

maximum values are measured under worst case conditions. The timing numbers in the following sections are

obtained using a simulation that assumes a model as shown in Figure 6.

Table 19. DDR SDRAM Output Driver Specifications

Signal Path

Output Current (mA)

I/O H (maximum)

I/O L (maximum)

Write Data

MemData00:31

ECC0:7

DM0:4

MemClkOut

MemAddr00:14

BA0:2

RAS

CAS

BankSel0:1

MemClkEn

DQS0:4

MemODT0:1

Table 20. DDR SDRAM Write Operation Conditions

Case

Process Speed

Junction Temperature (°C)

Voltage (V)

Best

Fast

−40

+1.3

Worst

Slow

+125

+1.1

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