HT36A4 datasheet(9/38 Pages) HOLTEK

9 / 38 page

HT36A4

Rev. 1.10

March 12, 2007

Accumulator

The accumulator closely relates to ALU operations. It is

mapped to location 05H of the data memory and it can

operate with immediate data. The data movement be-

tween two data memory locations must pass through

the accumulator.

Arithmetic and Logic Unit

- ALU

This circuit performs 8-bit arithmetic and logic operation.

The ALU provides the following functions:

· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)

· Logic operations (AND, OR, XOR, CPL)

· Rotation (RL, RR, RLC, RRC)

· Increment & Decrement (INC, DEC)

· Branch decision (SZ, SNZ, SIZ, SDZ ....)

The ALU not only saves the results of a data operation but

can also change the status register.

Status Register

- STATUS

This 8-bit register (0AH) contains the zero flag (Z), carry

flag (C), auxiliary carry flag (AC), overflow flag (OV),

power down flag (PDF) and Watchdog time-out flag

(TO). It also records the status information and controls the

operation sequence.

With the exception of the TO and PDF flags, bits in the

status register can be altered by instructions like any

other register. Any data written into the status register

will not change the TO or PDF flags. In addition it should

be noted that operations related to the status register

may give different results from those intended. The TO

and PDF flags can only be changed by system power

up, Watchdog Timer overflow, executing the HALT in-

struction and clearing the Watchdog Timer.

The Z, OV, AC and C flags generally reflect the status of

the latest operations.

In addition, on entering the interrupt sequence or exe-

cuting a subroutine call, the status register will not be

automatically pushed onto the stack. If the contents of

status are important and the subroutine can corrupt the

status register, the programmer must take precautions

to save it properly.

Interrupt

The HT36A4 provides two internal Timer Counter inter-

rupts on each bank. The Interrupt Control register

(INTC;0BH) contains the interrupt control bits that sets

the enable/disable and the interrupt request flags.

Once an interrupt subroutine is serviced, all other inter-

rupts will be blocked (by clearing the EMI bit). This

scheme may prevent any further interrupt nesting. Other

interrupt requests may occur during this interval but only

the interrupt request flag is recorded. If a certain inter-

rupt needs servicing within the service routine, the pro-

grammer may set the EMI bit and the corresponding bit

of the INTC to allow interrupt nesting. If the stack is full,

the interrupt request will not be acknowledged, even if

the related interrupt is enabled, until the Stack Pointer is

decremented. If immediate service is desired, the stack

must be prevented from becoming full.

0 0 H

0 1 H

0 2 H

0 3 H

0 4 H

0 5 H

0 6 H

0 7 H

0 8 H

0 9 H

0 A H

0 B H

0 C H

0 D H

0 E H

0 F H

1 0 H

1 1 H

1 2 H

1 3 H

1 4 H

1 5 H

1 6 H

1 7 H

1 8 H

1 9 H

1 A H

1 B H

1 C H

1 D H

1 E H

1 F H

2 0 H

2 1 H

2 2 H

2 3 H

2 4 H

2 5 H

2 6 H

2 7 H

2 9 H

2 A H

2 B H

2 F H

F F H

G e n e r a l P u r p o s e

D a t a M e m o r y

( 2 0 8 B y t e s )

2 8 H

3 0 H

S p e c i a l P u r p o s e

D a t a M e m r o y

: U n u s e d .

R e a d a s " 0 0 "

W a v e t a b l e

F u n c t i o n

R e g i s t e r

I n d i r e c t A d d r e s s i n g R e g i s t e r 0

M P 0

I n d i r e c t A d d r e s s i n g R e g i s t e r 1

M P 1

A C C

P C L

T B L P

T B L H

W D T S

S T A T U S

I N T C

T M R 0 L

T M R 0 C

T M R 1 L

T M R 1 C

P A

P A C

P F

D A C H i g h B y t e ( D A H )

D A C L o w B y t e ( D A L )

D A C C o n t r o l ( D A C )

C h a n n e l N u m b e r S e l e c t ( C H A N )

F r e q u e n c y N u m b e r H i g h B y t e ( F r e q N H )

F r e q u e n c y N u m b e r L o w B y t e ( F r e q N L )

S t a r t A d d r e s s H i g h B y t e ( A d d r H )

S t a r t A d d r e s s L o w B y t e ( A d d r L )

R e p e a t N u m b e r H i g h B y t e ( R e H )

R e p e a t N u m b e r L o w B y t e ( R e L )

V o l u m e C o n t r o l H i g h ( V o l H )

V o l u m e C o n t r o l L o w ( V o l L )

RAM Mapping

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