HT36A4 datasheet(11/38 Pages) HOLTEK

11 / 38 page

HT36A4

Rev. 1.10

March 12, 2007

On the other hand, if the crystal oscillator is selected, a

crystal across OSC1 and OSC2 is needed to provide the

feedback and phase shift required for the oscillator, and

no other external components are required. A resonator

may be connected between OSC1 and OSC2 to replace

the crystal and to get a frequency reference, but two ex-

ternal capacitors in OSC1 and OSC2 are required.

The WDT oscillator is a free running on-chip RC oscilla-

tor, and no external components are required. Even if

the system enters the power down mode, the system

clock is stopped, but the WDT oscillator still works with a

period of approximately 78

ms. The WDT oscillator can

be disabled by mask option to conserve power.

Watchdog Timer

- WDT

The WDT clock source is implemented by a dedicated

RC oscillator (WDT oscillator) or instruction clock (sys-

tem clock of the MCU divided by 4), determined by mask

options. This timer is designed to prevent a software

malfunction or sequence jumping to an unknown loca-

tion with unpredictable results. The Watchdog Timer can

be disabled by mask option. If the Watchdog Timer is

disabled, all the executions related to the WDT result in

no operation.

Once the internal WDT oscillator (RC oscillator with a

period of 78

ms normally) is selected, it is first divided by

256 (8-stages) to get the nominal time-out period of ap-

proximately 20ms. This time-out period may vary with

temperature, VDD and process variations. By invoking

the WDT prescaler, longer time-out periods can be real-

ized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the

WDTS) can give different time-out periods. If WS2,

WS1, WS0 all equal to 1, the division ratio is up to 1:128,

and the maximum time-out period is 2.6 seconds.

If the WDT oscillator is disabled, the WDT clock may still

come from the instruction clock and operate in the same

manner except that in the HALT state the WDT may stop

counting and lose its protecting purpose. In this situation

the logic can only be restarted by external logic. The

high nibble and bit 3 of the WDTS are reserved for user

defined flags, and the programmer may use these flags

to indicate some specified status.

Bit No.

Label

Function

EMI

Controls the Master (Global) interrupt (1=enabled; 0=disabled)

Unused bit, read as

²0²

ET0I

Controls the Timer Counter 0 interrupt (1=enabled; 0=disabled)

ET1I

Controls the Timer Counter 1 interrupt (1=enabled; 0=disabled)

Unused bit, read as

²0²

T0F

Internal Timer Counter 0 request flag (1=active; 0=inactive)

T1F

Internal Timer Counter 1 request flag (1=active; 0=inactive)

Unused bit, read as

²0²

INTC (0BH) Register

C r y s t a l O s c i l l a t o r

R C O s c i l l a t o r

O S C 1

O S C 2

f O S C / 8

O S C 1

V D D

System Oscillator

8 - b i t C o u n t e r

W D T P r e s c a l e r

7 - b i t C o u n t e r

8 - t o - 1 M U X

W D T T i m e - o u t

W S 0 ~ W S 2

M a s k

O p t i o n

S e l e c t

W D T

O S C

f O S C / 8

Watchdog Timer

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