MPC8280 datasheet(393/1386 Pages) FREESCALE

393 / 1386 page

PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

9-85

Table 9-64 describes MUCR fields.

9.12.3.4.8

Queue Base Address Register (QBAR)

This register specifies the beginning of the circular queue structure in local memory. The following QBAR

should be accessed only from the 60x bus and only in agent mode. Accesses while in host mode or from

the PCI bus have undefined results.

Figure 9-80. Queue Base Address Register (QBAR)

Table 9-65 describes QBAR fields.

Table 9-64. MUCR Field Descriptions

Bits

Name

Access

Description

31–6

—

Reserved, should be cleared.

5–1

CQS

Circular queue size. CQS refers to each individual queue, not the total size of all four

queues together.

00001 4K entries (16 Kbytes)

00010 8K entries (32 Kbytes)

00100 16K entries (64 Kbytes)

01000 32K entries (128 Kbytes)

10000 64K entries (256 Kbytes)

All others reserved.

CQE

Circular queue enable. When set will allow PCI masters to access the inbound and

outbound queue ports. Writes are ignored and reads will return 0xFFFF_FFFF when

this bit is cleared. Normally, this bit is set only if software has initialized all pointers and

configuration registers.

Field

QBA

—

Reset

0000_0000_0000_0000

R/W

Addr

0x104F2

Field

—

Reset

0000_0000_0000_0000

R/W

Addr

0x104F0

Table 9-65. QBAR Field Descriptions

Bits

Name

Access

Description

31–20

QBA

Queue base address. Base address of circular queue in local memory. It must be

aligned to a 1Mbyte boundary.

19–0

—

Reserved, should be cleared.

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