MPC8280 datasheet(397/1386 Pages) FREESCALE

397 / 1386 page

PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

9-89

•

PCI-memory-to-60x-memory transfers—The DMA controller initiates reads on the PCI bus and

stores the data in the DMA queue. Once sufficient data is stored in the queue, a 60x memory write

is initiated. The DMA controller stops the transfer either for an error condition on the PCI bus or

60x bus, or when no data is left to transfer. Reading from PCI memory and writing to 60x memory

can occur concurrently.

•

60x-memory-to-PCI-memory transfers—The DMA controller initially fetches data from 60x

memory into the DMA queue. As soon as the first data arrives into the queue, the DMA engine

initiates write transactions to PCI memory. The DMA controller stops the transfer either when

there is an error on the PCI bus or 60x bus, or there is no more data left to transfer. Reading from

60x memory and writing to PCI memory can occur concurrently.

•

60x-memory-to-60x-memory transfers—The DMA controller begins reading data from 60x

memory and storing it in the DMA queue. Once sufficient data is stored in the queue, the DMA

controller begins writing data to 60x memory space beginning at the destination address. The

process is repeated until there is no more data to transfer or an error condition has occurred while

accessing memory.

9.13.1.6

DMA Registers

Each DMA channel has a set of seven 32-bit registers (mode, status, current descriptor address, next

descriptor address, source address, destination address, and byte count) to support transactions. This

section describes the format of the DMA support registers.

9.13.1.6.1

DMA Mode Registers 0–3 (DMAMR

The mode register allows software to start the DMA transfer and to control various DMA transfer

characteristics.

Figure 9-82. DMA Mode Registers 0–3 (DMAMR

Field

—

BWC

DM_SEN IRQS

—

DAHTS

Reset

0000_0000_0000_0000

R/W

Addr

0x10502 (DMAMR0); 0x10582 (DMAMR1); 0x10602 (DMAMR2); 0x10682 (DMAMR3)

3210

Field

SAHTS

DAHE SAHE

PRC

—

EOTIE

—TEM CTM

Reset

0000_0000_0000_0000

R/W

Addr

0x10500 (DMAMR0); 0x10580 (DMAMR1); 0x10600 (DMAMR2); 0x10680 (DMAMR3)

MPC8280 데이터시트(PDF) 397 Page - Freescale Semiconductor, Inc

MPC8280 데이터시트(HTML) 397 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL