MPC8280 datasheet(402/1386 Pages) FREESCALE

402 / 1386 page

PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

9-94

Freescale Semiconductor

9.13.1.6.5

DMA Destination Address Registers 0–3 (DMADAR

The destination address register, shown in Figure 9-86, indicates the address where the DMA controller

will be writing data to. This address can be in either PCI memory or 60x memory. The software has to

ensure that this is a valid memory address.

The choice between PCI or 60x is done according to the following rule: If the address hits one of the PCI

outbound windows, then the destination data is written to the PCI memory. Otherwise, it is written to the

60x memory. Refer to Figure 9-13.

Figure 9-86. DMA Destination Address Registers 0–3 (DMADAR

Table 9-70 describes DMADARx fields.

9.13.1.6.6

DMA Byte Count Registers 0–3 (DMABCR

This register contains the number of bytes per transfer (maximum transfer size is 64 Mbytes).

Field

Reset

0000_0000_0000_0000

R/W

Addr

0x1051A (DMAADAR0); 0x1059A (DMAADAR1); 0x1061A (DMAADAR2); 0x1069A (DMAADAR3)

Field

Reset

0000_0000_0000_0000

R/W

Addr

0x10518 (DMAADAR0); 0x10598 (DMAADAR1); 0x10618 (DMAADAR2); 0x10698 (DMAADAR3)

Table 9-70. DMADAR

x Field Descriptions

Bit

Name

Description

31–0

Destination address. The content is updated after every DMA write operation.

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