MPC8280 datasheet(403/1386 Pages) FREESCALE

403 / 1386 page

PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

9-95

Figure 9-87. DMA Byte Count Registers 0–3 (DMABCR

Table 9-71 describes DMABCRx fields.

9.13.1.6.7

DMA Next Descriptor Address Registers 0–3 (DMANDAR

The next descriptor address register (NDAR) contains the address for the next segment descriptor in the

chain. In chaining mode, this register is loaded from the “next descriptor” field of the descriptor that the

current descriptor register is pointing to. Refer to Figure 9-89.

Figure 9-88. DMA Next Descriptor Address Registers 0–3 (DMANDAR

Field

—

Reset

0000_0000_0000_0000

R/W

Addr

0x10522 (DMABCR0); 0x105A2(DMABCR1); 0x10622 (DMABCR2); 0x106A2 (DMABCR3)

Field

Reset

0000_0000_0000_0000

R/W

Addr

0x10520 (DMABCR0); 0x105A0 (DMABCR1); 0x10620 (DMABCR2); 0x106A0 (DMABCR3)

Table 9-71. DMABCR

x Field Descriptions

Bit

Name

Description

31–26

—

Reserved, should be cleared.

25–0

Byte count. Contains the number of bytes to transfer. The value in this register is

decremented after each DMA read operation.

Field

NDA

Reset

0000_0000_0000_0000

R/W

Addr

0x10526 (DMANDAR0); 0x105A6 (DMANDAR1); 0x10626 (DMANDAR2); 0x106A6 (DMANDAR3)

Field

NDA

NDSNE

NDEOSIE

—EOTD

Reset

0000_0000_0000_0000

R/W

Addr

0x10524 (DMANDAR0); 0x105A4 (DMANDAR1); 0x10624 (DMANDAR2); 0x106A4 (DMANDAR3)

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