MPC8280 datasheet(540/1386 Pages) FREESCALE

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IEEE 1149.1 Test Access Port

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

13-6

Freescale Semiconductor

parallel outputs during the update-IR controller state. The four bits are used to decode the five unique

instructions listed in Table 13-2.

Table 13-2. Instruction Decoding

Code1

Instruction

Description

EXTEST

External test. Selects the 475-bit boundary scan register.

EXTEST also asserts an internal reset for the MPC8280’s

system logic to force a known beginning internal state while

performing external boundary scan operations. By using the

TAP, the register is capable of scanning user-defined values

into the output buffers, capturing values presented to input

pins, sampling this data into the boundary scan register (device

revision B.3 and later), and controlling the output drive of

three-state output or bidirectional pins. For more details on the

function and use of EXTEST, refer to the IEEE 1149.1

standard.

SAMPLE/

PRELOAD

Initializes the boundary scan register output cells before the

selection of EXTEST. This initialization ensures that known

data appears on the outputs when entering an EXTEST

instruction. SAMPLE/PRELOAD also provides a chance to

obtain a snapshot of system data and control signals.

NOTE: Since there is no internal synchronization between the

TCK and CLKOUT, the user must provide some form of

external synchronization between the JTAG operation at TCK

frequency and the system operation CLKOUT frequency to

achieve meaningful results.

BYPASS

The BYPASS instruction creates a shift register path from TDI

to the bypass register and, finally, to TDO, circumventing the

475-bit boundary scan register. This instruction is used to

enhance test efficiency when a component other than the

MPC8280 becomes the device under test. It selects the

single-bit bypass register as shown below.

When the bypass register is selected by the current instruction,

the shift register stage is cleared on the rising edge of TCK in

the capture-DR controller state. Thus, the first bit to be shifted

out after selecting the bypass register is always a logic zero.

MUX

To TDO

From TDI

Shift DR

Clock DR

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