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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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MPC8280 데이터시트(PDF) 701 Page - Freescale Semiconductor, Inc |
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MPC8280 데이터시트(HTML) 701 Page - Freescale Semiconductor, Inc |
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701 / 1386 page  Serial Communications Controllers (SCCs) MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 20-21 20.3.6 Digital Phase-Locked Loop (DPLL) Operation Each SCC channel includes a digital phase-locked loop (DPLL) for recovering clock information from a received data stream. For applications that provide a direct clock source to the SCC, the DPLL can be bypassed by selecting 1x mode for GSMR_L[RDCR, TDCR]. If the DPLL is bypassed, only NRZ or NRZI encodings are available. The DPLL must not be used when an SCC is programmed to Ethernet and is optional for other protocols. Figure 20-13 shows the DPLL receiver block; Figure 20-14 shows the transmitter block diagram. Figure 20-13. DPLL Receiver Block Diagram DPLL HSRCLK RXD RINV TSNC EDGE RDCR RENC Receiver Carrier SNC Decoded Data Hunting Noise 0 S Recovered Clock HSRCLK RCLK 1 1x Mode 0 S SCCR Data 1 1x Mode D CLK Q HSRCLK RXD RINV RENC ≠ NRZI |
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