MPC8280 datasheet(1238/1386 Pages) FREESCALE

1238 / 1386 page

Fast Ethernet Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

36-4

Freescale Semiconductor

— Overrun

— Busy (out of buffers)

•

Error counters

— Discarded frames (out of buffers or overrun occurred)

— CRC errors

— Alignment errors

•

Internal and external loopback mode

•

Supports Fast Ethernet in duplex mode

•

Supports pause flow control frames

•

Support of out-of-sequence transmit queue (for flow-control frames)

•

External buffer descriptors (BDs)

36.3

Connecting the MPC8280 to Fast Ethernet

Figure 36-3 shows the basic components of the media-independent interface (MII) and the signals required

to make the Fast Ethernet connection between the MPC8280 and a PHY.

Figure 36-3. Connecting the MPC8280 to Ethernet

Transmit Error (TX_ER)

Transmit Nibble Data 0–3 (TXD[0–3])

Transmit Enable (TX_EN)

Transmit Clock (TX_CLK)

Collision Detect (COL)

Receive Nibble Data (RXD[0–3])

Receive Error (RX_ER)

Receive Clock (RX_CLK)

Receive Data Valid (RX_DV)

Carrier Sense Output (CRS)

Management Data I/O1 (MDIO)

Management Data Clock1 (MDC)

MPC8280

Fast Ethernet

PHY

Medium

Media-Independent Interface (MII)

1 The management signals (MDC and MDIO) can be common to all of the Fast Ethernet connections in

the system, assuming that each PHY has a different management address. Use parallel I/O port pins to

implement MDC and MDIO. (The I2C controller cannot be used for this function.)

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