MPC8280 datasheet(1239/1386 Pages) FREESCALE

1239 / 1386 page

Fast Ethernet Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

36-5

Each FCC has 18 signals, defined by the IEEE 802.3u standard, for connecting to an Ethernet PHY. The

two management signals (MDC and MDIO) required by the MII should be implemented separately using

the parallel I/O.

The MPC8280 has additional signals for interfacing with an optional external content-addressable memory

(CAM), which are described in Section 36.7, “CAM Interface.”

The MPC8280 uses the SDMA channels to store every byte received after the start frame delimiter into

system memory. On transmit, the user provides the destination address, source address, type/length field,

and transmit data. To meet minimum frame requirements, MPC8280 automatically pads frames with fewer

than 64 bytes in the data field. The MPC8280 also appends the FCS to the frame.

36.3.1

Connecting the MPC8280 to Ethernet (RMII)

Figure 36-4 shows the basic components of the reduced media-independent interface (RMII) and the

signals required for the fast Ethernet connection between the MPC8280 and a PHY. The MDC/MDIO

management interface is the same as in MII. The RMII reference clock (REF_CLK) is distributed over the

FCC transmit clock. In RMII mode receive clock is not used.

Figure 36-4. Connecting the

MPC8280 to Ethernet (RMII)

36.4

Ethernet Channel Frame Transmission

The Ethernet transmitter requires almost no core intervention. When the core enables the transmitter, the

Ethernet controller polls the first TxBD in the FCC’s TxBD table every 256 serial clocks. If the user has a

frame ready to transmit, setting FTODR[TOD] eliminates waiting for the next poll. When there is a frame

to transmit, the Ethernet controller begins fetching the data from the data buffer and asserts TX_EN. The

preamble sequence, start frame delimiter, and frame information are sent in that order; see Figure 36-1. In

full-duplex mode, because collisions are ignored, frame transmission maintains only the interframe gap 28

serial clocks (112 bit time period) regardless of CRS assertion.

Transmit di-bit Data (TXD[1:0])

Transmit Enable (TX_EN)

Reference Clock (REF_CLK)

Receive di-bit Data (RXD[1:0])

Receive Error (RX_ER)

Receive CRS_DV (CRS_DV)

Management Data I/O 1 (MDIO)

Management Data Clock1 (MDC)

MPC8280

Fast Ethernet

RMII PHY

Medium

1The management signals (MDC and MDIO) can be common to all of the fast Ethernet connections in the

system, assuming that each PHY has a different management address. Use parallel I/O port pins to implement

MDC and MDIO. (The I2C controller cannot be used for this function.)

Clock from board

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