MU9C8328 Ethernet Interface

Rev. 4a

8

L ANCAM

M U 9C 8328

A M 79C 940

S RDC LK

SRD

/E AM /R

/E

/E C

/M F

/FF

DQ (15- 0)

/CM

/W

D(15- 0)

RE ADY

/CS

/W E

/RESE T

A(2-0)

S E RCLK

S E RDAT

/REJEC T

/INT

SYSCLK

/AS

TXEN

/NETRD Y

/E

/E C

/M F

/FF

/CM

/W

L ANCAM

M U 9C 8328

D P 8 3932

RX Co

RX Do

/P RE J

/E

/E C

/M F

/FF

DQ (15- 0)

/CM

/W

D(15- 0)

RE ADY

/CS

/W E

/RESE T

A(2-0)

S E RCLK

S E RDAT

/REJEC T

/INT

SYSCLK

/AS

TX E

/NE TRD Y

/E

/E C

/M F

/FF

/CM

/W

Connections

Connection diagrams are shown in Figures 2, 3, and 4 for

National’s SONIC, AMD’s MACE, and Motorola’s

QUICC Ethernet controller chips. Other controller chips

that provide a serial NRZ received data port and clock

can also be used in similar fashions. The /NETRDY line

is provided for controller chips that output data on the

received data line while transmitting. If /NETRDY is

deasserted, the internal network state machine will safely

complete any current activity and then wait until

/NETRDY is asserted again before parsing another frame.

If the controller chip does not output data on the received

data line while transmitting, /NETRDY may be tied to

ground, and the MU9C8328’s valid clock detector will

determine when it is time to start parsing a frame.

Initialization of the LANCAM

Before using, the MUSIC LANCAMs need to be configured

for the number of LANCAMs in a daisy chain and for the

filtering conditions in the Control and Segment Control

registers. Before configuring the LANCAMs, bit 13 in the

MU9C8328 Control register needs to be set to 0, to turn off

network filtering. Table 3 shows the steps for configuring

two LANCAMs in a daisy chain. The routine selects register

05H in the MU9C8328, which sends Command Write cycles

to the LANCAM. The sequence shown resets the LANCAMs,

sets the Page address for both LANCAMs in the daisy chain,

then sets the Control and Segment Control registers. If a

Mask register were needed, then the sequence would be

modified to set the Persistent destination to MR1 or MR2,

use MU9C8328 register 06H to write data into the Mask

register, change the final Control register value to 8050H or

8060H instead of 8040H to invoke MR1 or MR2 during

compares, and then resetting the Persistent destination to

APPLICATIONS

Figure 4: Motorola’s QUICC™ Connection Diagram

Figure 2: AMD’s MACE™ Connection Diagram

Figure 3: National’s SONIC™ Connection Diagram

L ANCAM

M U 9C 8328

/E

/E C

/M F

/FF

DQ (15- 0)

/CM

/W

D(15- 0)

RE ADY

/CS

/W E

/RESE T

A(2-0)

S E RCLK

S E RDAT

/REJEC T

/INT

SYSCLK

/AS

M C 68160

EE ST

M C 68360

QUIC C

RX

RX D

/RR JCT

RCL K

RCL K

RE NA

RE NA

/NE TRD Y

/E

/E C

/M F

/FF

/CM

/W