MU9C8328 Ethernet Interface

Rev. 4a

12

PROCESSOR INTERFACE WRITE CYCLE

CLOCK TIMING

NOTES

1.

-1.0 Volts for a duration of 10 ns measured at the 50% amplitude points for imput-only lines (Figure 7)

2.

Plus one SERCLK cycle from the first SERCLK HIGH pulse

3.

Before first network data pulse

4.

From the SYSCLK that strobed the last DA or SA segment into the LANCAM

5.

LANCAM Controls include /W, /CM, and /EC

6.

See the LANCAM Handbook for additional information on LANCAM Timing Specs

7.

With load specified in Figure 5

8.

With load specified in Figure 6

SYSCL K

S E RCL K

SENSE

1

2

3

45

7

6

8

10

9

SYSCLK

/CS

/AS

A(2-0)

/W E

D(15- 0)

RE ADY

11

11

14

15

16

19

20

21

22

18

12

12

13

13

17

23