ADS1174IPAPR datasheet(14/35 Pages) TI

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VOLTAGE REFERENCE INPUTS

CLOCK INPUT (CLK)

ESD

Protection

AVDD

VREFN

VREFP

AGND

VREFP

VREFN

eff

´ (6.75MHz/f

)

MOD

5.2kW

N =numberofactivechannels.

ADS1174

ADS1178

SBAS373 – OCTOBER 2007

If these conditions are possible, external Schottky

(VREFP, VREFN)

clamp diodes or series resistors may be required to

limit the input current to safe levels (see Absolute

The voltage reference for the ADS1174/78 ADC is

Maximum Ratings table).

the differential voltage between VREFP and VREFN:

VREF = (VREFP – VREFN). The voltage reference is

Note that the valid operating range of the reference

common to the four channels. The reference inputs

inputs is limited to the following:

use a structure similar to that of the analog inputs

–0.1V

≤ VREFN ≤ VREFP – 0.5V

with the equivalent circuitry on the reference inputs

shown in Figure 10. As with the analog inputs, the

VREFN + 0.5V

≤ VREFP ≤ AVDD + 0.1V

load presented by the switched capacitor can be

A high-quality reference voltage with the appropriate

modeled with an effective impedance, as shown in

drive strength is essential for achieving the best

Figure 11. However, the reference input impedance

performance from the ADS1174/78. Noise and drift

depends on the number of active (enabled) channels

the

reference

degrade

overall

system

in addition to fMOD. As a result of the change of

performance. See the Application Information section

reference input impedance caused by enabling and

for example reference circuits.

disabling channels, the regulation and settling time of

the external reference should be noted, so as not to

affect the readings of other channels.

The ADS1174/78 requires a clock input for operation.

Each ADS1174/78 converter operates from the same

clock input. At the maximum data rate, the clock input

can be either 27MHz or 13.5MHz (5.4MHz, low

power), determined by the setting of the CLKDIV

input. The selection of the external clock frequency

(fCLK) does not affect the resolution (the oversampling

ratio, OSR, remains fixed) or power dissipation of the

ADS1174/78. However, using a slower fCLK can

reduce the power consumption of an external clock

driver. The output data rate scales with clock

frequency, down to a minimum clock frequency of

fCLK = 100kHz. Table 5 summarizes the ratio of clock

input frequency (fCLK) to data rate (fDATA), maximum

data rate and corresponding maximum clock input for

Figure 10. Equivalent Reference Input Circuitry

the two operating modes.

Table 5. Clock Input Options

MODE

fCLK

DATA RATE

SELECTION

(MHz)

CLKDIV

fCLK/fDATA

(SPS)

512

High-Speed

52,734

13.5

256

2,560

Low-Power

10,547

5.4

512

As with any high-speed data converter, a high-quality,

Figure 11. Effective Reference Impedance

low-jitter clock is essential for optimum performance.

Crystal clock oscillators are the recommended clock

source. Make sure to avoid excess ringing on the

ESD diodes protect the reference inputs. To keep

clock input; keeping the clock trace as short as

these diodes from turning on, make sure the voltages

possible using a 50

Ω series resistor, placed close to

on the reference pins do not go below AGND by

the source end, often helps.

more than 0.4V, and likewise do not exceed AVDD by

0.4V.

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