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ADS1174IPAPR 데이터시트(PDF) 23 Page - Texas Instruments

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부품명 ADS1174IPAPR
상세설명  Quad/Octal, Simultaneous Sampling, 16-Bit Analog-to-Digital Converters
PDF  35 Pages
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제조업체  TI [Texas Instruments]
홈페이지  http://www.ti.com
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ADS1174IPAPR 데이터시트(HTML) 23 Page - Texas Instruments

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SYNC
DIN
DOUT1
SYNC
SCLK
FSYNC
SCLK
ADS1178
SYNC
DIN
CLK
CLK
FSYNC
DOUT1
SCLK
ADS1178
SYNC
DOUT1
SCLK
ADS1178
SYNC
DIN
FSYNC
DOUT1
SCLK
ADS1178
CLK
CLK
CLK
FSYNC
DIN
FSYNC
Serial
Data
from
Devices
1and2
Serial
Data
from
Devices
3and4
U4
U3
U2
U1
ADS1174
ADS1178
SBAS373 – OCTOBER 2007
To increase the number of data channels possible in
Whether the interface protocol is SPI or Frame-Sync,
a chain, a segmented DOUT scheme may be used,
it is recommended to synchronize all devices by tying
producing two data streams. Figure 23 illustrates four
the SYNC inputs together. When synchronized in SPI
ADS1178s, with a pair of ADS1178s daisy-chained
protocol, it is only necessary to monitor the DRDY
together. The channel data of each daisy-chained
output of one ADS1178.
pair is shifted out in parallel and is received by the
In Frame-Sync interface protocol, the data from all
processor through independent data channels.
devices are ready on the rising edge of FSYNC.
Since DOUT1 and DIN are both shifted on the falling
edge of SCLK, the propagation delay on DOUT1
creates a setup time for DIN. Minimize the skew in
SCLK to avoid timing violations.
Figure 23. Segmented DOUT Daisy-Chain, Frame-Sync Protocol (FORMAT[2:0] = 000 or 001)
Copyright © 2007, Texas Instruments Incorporated
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Product Folder Link(s): ADS1174 ADS1178



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