ADS1174IPAPR datasheet(19/35 Pages) TI

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DRDY/FSYNC (Frame-Sync Format)

FRAME-SYNC SERIAL INTERFACE

DOUT

SCLK

DIN

ADS1174

ADS1178

SBAS373 – OCTOBER 2007

In Frame-Sync format, this pin is used as the FSYNC

Frame-Sync format is similar to the interface often

input. The frame-sync input (FSYNC) sets the frame

used

audio

ADCs.

operates

slave

period which must be same as the data rate. The

fashion—the user must supply framing signal FSYNC

required number of fCLK cycles to each FSYNC period

(similar to the left/right clock on stereo audio ADCs)

depends on the mode selection and the CLKDIN

and the serial clock SCLK (similar to the bit clock on

input. Table 5 indicates the number of CLK cycles to

audio ADCs). The data is output MSB first or

each frame (fCLK/fDATA). If the FSYNC period is not

left-justified. When using Frame-Sync format, the

the proper value, data readback will be corrupted.

FSYNC and SCLK inputs must be continuously

running with the required relationships shown in the

Frame-Sync Timing Requirements.

In Discrete Data Output mode, the conversion data

are shifted out on the individual DOUT pins (DOUT1,

DOUT2, etc.), whereas in TDM mode, data are output

The serial clock (SCLK) features a Schmitt-triggered

only on DOUT1. The MSB data become valid on

input and shifts out data on DOUT on the falling

DOUT[4:1]/[8:1] on the SCLK rising edge prior to

edge. It also shifts in data on the falling edge on DIN

FSYNC going high. The subsequent bits are shifted

when this pin is being used for daisy-chaining. Even

out with each falling edge of SCLK. If daisy-chaining

though SCLK has hysteresis, it is recommended to

(TDM mode), the data shifted in using DIN will appear

keep SCLK as clean as possible to prevent glitches

on DOUT1 after all channel data have been shifted

from accidentally shifting the data. When using

out (that is, 4 channels

× 16 bits per channel = 64 bits

Frame-Sync format, SCLK must run continuously. If it

for the ADS1174, and 8 channels

× 16 bits per

is shut down, the data readback will be corrupted.

channel = 128 bits for the ADS1178).

The number of SCLKs within a frame period (FSYNC

clock) can be any power of two ratio of clock cycles

(1, 1/2, 1/4, etc.), as long as the number of cycles is

sufficient to shift the data output from all channels

This input is used when multiple ADS1174/78s are to

within one data frame.

be daisy-chained together. It can be used with either

SPI or Frame-Sync formats. Data are shifted in on

the falling edge of SCLK. When using only one

ADS1174/78, tie DIN low. See the Daisy-Chaining

section for more information.

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