TMPR4937 datasheet(104/552 Pages) TOSHIBA

104 / 552 page

Chapter 7 External Bus Controller

7-4

7.3.2

Global/Boot-up Options

In addition to the settings made separately for each channel, the Channel Control Registers can also

use global options that make settings common to all channels.

External Bus Controller Channel 0 can be used as a Boot memory channel. Channel 0 is set by the

external pins (Boot pins) during reset.

These settings are summarized below in Table 7.3.1. (Please refer to “3.3 Configuration signals” and

“5.2.1 Chip Configuration Register” for more information.)

Table 7.3.1 Global/Boot-up Options

Pin Name

Set Register

Explanation

⎯

CCFG.ARMODE

Selects the operation mode of the ACK*/READY signal.

0 = ACK*/READY Dynamic mode (Default)

1 = ACK*/READY Static mode

⎯

CCFG.ACEHOLD

Sets the address hold time relative to the ACE* signal.

0: Address changes simultaneous to deassertion of the ACE* signal.

1: Address changes 1 clock cycle after deassertion of the ACE* signal.

(Default)

ADDR[14:13]

CCFG.SYSSP

Specifies the division ratio of the SYSCLK output relative to the internal

bus clock (GBUSCLK).

00: 1/4 speed (1/4 the GBUSCLK frequency)

01: 1/3 speed (1/3 the GBUSCLK frequency)

10: 1/2 speed (1/2 the GBUSCLK frequency)

11: Full speed (same frequency as the GBUSCLK frequency)

ADDR[8]

EBCCR0.ME

Specifies whether to enable or disable Channel 0.

0: Disable this channel as a Boot channel.

1: Enable this channel as a Boot channel.

ADDR[7:6]

EBCCR0.SP

Specifies the operation speed of Channel 0.

00: 1/4 Speed mode

01: 1/3 Speed mode

10: 1/2 Speed mode

11: Full Speed mode

DATA[5]

EBCCR0.BC

When accessing Channel 0, specifies whether to use the BWE[3:0] signal

as a Byte Enable signal (BE[3:0]) or to use it as a Byte Write Enable

signal (BWE[3:0]).

0: Byte Enable mode

1: Byte Write Enable mode

DATA[4]

EBCCR0.WT[0]

Specifies the Channel 0 access mode.

0: Normal mode (DATA[4] = H)

1: External ACK mode (DATA[4] = L)

DATA[1:0]

EBCCR0.BSZ

Specifies the memory bus width of Channel 0.

00: Reserved

01: 32-bit width

10: 16-bit width

11: 8-bit width

TMPR4937 데이터시트(PDF) 104 Page - Toshiba Semiconductor

TMPR4937 데이터시트(HTML) 104 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL