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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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LSM6DSV320X 데이터시트(PDF) 29 Page - STMicroelectronics |
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LSM6DSV320X 데이터시트(HTML) 29 Page - STMicroelectronics |
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29 / 212 page  Command Command code Default Description GETMRL 0x8C 0x00 0x10 0x0A (3 byte) Get maximum read length during private read GETPID 0x8D 0x02 0x08 0x00 0x73 0x92 0x0B SDO = 1 0x02 0x08 0x00 0x73 0x12 0x0B SDO = 0 GETBCR 0x8E 0x27 (1 byte) Bus characteristics register GETDCR 0x8F 0x44 default MIPI I3C® device characteristics register GETSTATUS 0x90 0x00 0x00 (2 byte) Status register GETMXDS 0x94 0x08 0x60 Return max write and read speed GETCAPS 0x95 0x00 0x11 0x18 0x00 Provide information about device capabilities and supported extended features SETGRPA 0x9B Group address assignment command RSTGRPA 0x2C / 0x9C Reset the group address RSTACT 0x9A / 0x2A Configure target reset action 5.2.3 Overview of antispike filter management The device acts as a standard I²C target as long as it has an I²C static address. The device is capable of detecting and disabling the I²C antispike filter after detecting the broadcast address (7'h7E/W). In order to guarantee proper behavior of the device, the I3C controller must emit the first START, 7'h7E/W at open-drain speed using I²C fast mode plus reference timing. After detecting the broadcast address, the device can receive the I3C dynamic address following the I3C push- pull timing. If the device is not assigned a dynamic address, then the device continues to operate as an I²C device with no antispike filter. For the case in which the host decides to keep the device as I²C with an antispike filter, there is a configuration required to keep the antispike filter active. This configuration is done by writing the ASF_CTRL bit to 1 in the IF_CFG (03h) register. This configuration forces the antispike filter to always be turned on instead of being managed by the communication on the bus. LSM6DSV320X Digital interfaces DS14623 - Rev 1 page 29/212 |
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