M29W400DT datasheet(13/48 Pages) STMICROELECTRONICS

13 / 48 page

M29W400DT, M29W400DB

Signal descriptions

13/48

Signal descriptions

See Figure 1: Logic diagram, and Table : , for a brief overview of the signals connected to

this device.

2.1

Address inputs (A0-A17)

The Address inputs select the cells in the memory array to access during Bus Read

operations. During Bus Write operations they control the commands sent to the command

interface of the Program/Erase controller.

2.2

Data inputs/outputs (DQ0-DQ7)

The Data inputs/outputs output the data stored at the selected address during a Bus Read

operation. During Bus Write operations they represent the commands sent to the command

interface of the Program/Erase controller.

2.3

Data inputs/outputs (DQ8-DQ14)

The Data inputs/outputs output the data stored at the selected address during a Bus Read

operation when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are

high impedance. During Bus Write operations the Command Register does not use these

bits. When reading the Status Register these bits should be ignored.

2.4

Data input/output or Address input (DQ15A-1)

When BYTE is High, VIH, this pin behaves as a Data input/output pin (as DQ8-DQ14). When

BYTE is Low, VIL, this pin behaves as an address pin; DQ15A–1 Low will select the LSB of

the word on the other addresses, DQ15A–1 High will select the MSB. Throughout the text

consider references to the Data input/output to include this pin when BYTE is High and

references to the Address inputs to include this pin when BYTE is Low except when stated

explicitly otherwise.

2.5

Chip Enable (E)

The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to

be performed. When Chip Enable is High, VIH, all other pins are ignored.

2.6

Output Enable (G)

The Output Enable, G, controls the Bus Read operation of the memory.

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