ISL73847SEHDEMO2Z datasheet(5/40 Pages) RENESAS

5 / 40 page

R34DS0017EU0104 Rev.1.04

Page 5

Jan 31, 2025

ISL73041SEH Datasheet

6AVCC

The output of the internal 5V LDO regulator for chip bias. Input is VDD. A minimum of 1µF

ceramic decoupling capacitor is necessary on AVCC to SGND.

VDD

Input supply to chip. Recommended bias range is 4.75V to 18V.

8FB

PVCC LDO error amplifier inverting input. A resistor divider network from FB to PVCC and

SGND sets the PVCC LDO output voltage. If FB is connected to PVCC, PVCC output voltage

is 4.5V.

9PVCC

Output of the LDO for the gate drive voltage. Recommended PVCC range is 4.5V to 5.5V. A

minimum 1µF ceramic decoupling capacitor is necessary on PVCC to PGND.

PGND

Low-side driver output reference pin. For typical applications, connect PGND to ground plane

and SGND (PAD). Alternatively, connect PGND directly to the low-side transistor's source

terminal.

LGL

Low-side sink driver for gate turn-off. Connect this pin to LGH and the GaN FET gate.

LGH

Low-side source driver for gate turn-on. Connect this pin to LGL and the GaN FET gate.

PHS

High-side GaN FET source reference. Connect to the phase switching node of the half-

bridge.

UGL

High-side sink driver for gate turn-off. Connect this pin to UGH and the GaN FET gate.

UGH

High-side source driver for gate turn-on. Connect this pin to UGL and the GaN FET gate.

BOOT

High-side bootstrap bias pin. Connect a bootstrap capacitor from this pin to PHS. An internal

bootstrap switch connects PVCC to BOOT when PWM = 0V and PHS voltage is within

250mV of PGND.

PAD

SGND

Analog signal GND and package bottom thermal pad. The die substrate is electrically

connected to PAD. Connect to the ground plane.

LID

SGND

The package lid is internally connected to the four bottom pads, die substrate and SGND.

Number

Pin Name

ESD

Circuit

Description

PGND

Package

PVCC

Package

0.7V

Clamp

0.7V

Clamp

PHS

Package

BOOT

Package

0.7V

Clamp

Circuit 4

Circuit 5

Circuit 6

Circuit 7

0.7V

Clamp

PGND

PHS

PGND

Package

9.6V

Clamp

28.8V

Clamp

BOOT

9.6V Clamp

28.8V

Clamp

Circuit 1

Circuit 2

Circuit 3

ISL73847SEHDEMO2Z 데이터시트(PDF) 5 Page - Renesas Technology Corp

ISL73847SEHDEMO2Z 데이터시트(HTML) 5 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

데이터시트 다운로드

링크 URL