MPC8358E datasheet(30/96 Pages) FREESCALE

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MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1

Freescale Semiconductor

UCC Ethernet Controller: Three-Speed Ethernet, MII Management

8.2.3

RMII AC Timing Specifications

This section describes the RMII transmit and receive AC timing specifications.

8.2.3.1

RMII Transmit AC Timing Specifications

Table 30 provides the RMII transmit AC timing specifications.

Figure 13 shows the RMII transmit AC timing diagram.

Figure 13. RMII Transmit AC Timing Diagram

Table 30. RMII Transmit AC Timing Specifications

At recommended operating conditions with LVDD / OVDD of 3.3 V ± 10%.

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

REF_CLK clock

tRMX

—20

—

REF_CLK duty cycle

tRMXH/tRMX

—

REF_CLK to RMII data TXD[1:0], TX_EN delay

tRMTKHDX

tRMTKHDV

—

——

REF_CLK data clock rise time, VIL(min) to VIH(max)

tRMXR

1.0

—

4.0

REF_CLK data clock fall time, VIH(max) to VIL(min)

tRMXF

1.0

—

4.0

Note:

1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state)

(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,

tRMTKHDX symbolizes RMII transmit timing (RMT) for the time tRMX clock reference (K) going high (H) until data

outputs (D) are invalid (X). Note that, in general, the clock reference symbol representation is based on two to three

letters representing the clock of a particular functional. For example, the subscript of tRMX represents the RMII(RM)

reference (X) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

REF_CLK

TXD[1:0]

tRMTKHDX

tRMX

tRMXH

tRMXR

tRMXF

TX_EN

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