MPC8358E datasheet(17/96 Pages) FREESCALE

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MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1

Freescale Semiconductor

DDR and DDR2 SDRAM

This section describes the DC and AC electrical specifications for the DDR and DDR2 SDRAM interface

of the MPC8358E.

6.1

DDR and DDR2 SDRAM DC Electrical Characteristics

Table 12 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the

device when GVDD(typ) = 1.8 V.

SPI (master/slave)

10 (max)

UCC through TDM

50 (max)

× F2

MCC

25 (max)

16.67

× F2, 4

UTOPIA L2

50 (max)

800

× F2

POS-PHY L2

50 (max)

800

× F2

HDLC Bus

10 (max)

HDLC/Transparent

50 (max)

8/3

× F2, 3

UART/Async HDLC

3.68 (max internal ref

clock)

115 (Kbps)

BISYNC

2 (max)

USB

48 (ref clock)

Note:

1. The QE needs to run at a frequency higher than or equal to what is listed in this table.

2. ‘F’ is the actual interface operating frequency.

3. The bit rate limit is independent of the data bus width (i.e. the same for serial, nibble, or octal

interfaces).

4. TDM in high-speed mode for serial data interface.

Table 12. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V

Parameter/Condition

Symbol

Min

Max

Unit

Notes

I/O supply voltage

GVDD

1.71

1.89

I/O reference voltage

MVREF

0.49

× GVDD

0.51

× GVDD

I/O termination voltage

VTT

MVREF – 0.04

MVREF + 0.04

Input high voltage

VIH

MVREF + 0.125

GVDD + 0.3

Input low voltage

VIL

–0.3

MVREF – 0.125

Output leakage current

IOZ

—±10

μA4

Output high current (VOUT = 1.420 V)

IOH

–13.4

—

Table 11. QE Operating Frequency Limitations (continued)

Interface

Interface Operating

Frequency (MHz)

Max interface

Bit Rate (Mbps)

Min QE Operating

Frequency1 (MHz)

Notes

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