LPC2917 datasheet(11/68 Pages) PHILIPS

11 / 68 page

LPC2917_19_1

Preliminary data sheet

Rev. 1.01 — 15 November 2007

11 of 68

NXP Semiconductors

LPC2917/19

ARM9 microcontroller with CAN and LIN

7.1.3 IEEE 1149.1 interface pins (JTAG boundary-scan test)

The LPC2917/19 contains boundary-scan test logic according to IEEE 1149.1, also

referred to in this document as Joint Test Action Group (JTAG). The boundary-scan test

pins can be used to connect a debugger probe for the embedded ARM processor. Pin

JTAGSEL selects between boundary-scan mode and debug mode. Table 5 shows the

boundary- scan test pins.

7.1.4 Power supply pins description

Table 6 shows the power supply pins.

7.2 Clocking strategy

7.2.1 Clock architecture

The LPC2917/19 contains several different internal clock areas. Peripherals like Timers,

SPI, UART, CAN and LIN have their own individual clock sources called Base Clocks. All

base clocks are generated by the Clock Generator Unit (CGU). They may be unrelated in

frequency and phase and can have different clock sources within the CGU.

The system clock for the CPU and AHB Multilayer Bus infrastructure has its own base

clock. This means most peripherals are clocked independently from the system clock. See

Figure 3 for an overview of the clock areas within the device.

Within each clock area there may be multiple branch clocks, which offers very flexible

control for power-management purposes. All branch clocks are outputs of the Power

Management Unit (PMU) and can be controlled independently. Branch clocks derived

from the same base clock are synchronous in frequency and phase. See Section 8.8 for

more details of clock and power control within the device.

Table 5.

IEEE 1149.1 boundary-scan test and debug interface

Symbol

Description

JTAGSEL

TAP controller select input. LOW level selects ARM debug mode and HIGH level

selects boundary scan and flash programming; pulled up internally

TRSTN

test reset input; pulled up internally (active LOW)

TMS

test-mode select input; pulled up internally

TDI

test data input, pulled up internally

TDO

test data output

TCK

test clock input

Table 6.

Power supplies

Symbol

Description

VDD(CORE)

digital core supply 1.8 V

VSS(CORE)

digital core ground (digital core, ADC 1)

VDD(IO)

I/O pins supply 3.3 V

VSS(IO)

I/O pins ground

VDD(OSC)

oscillator and PLL supply

VSS(OSC)

oscillator ground

VDD(A3V3)

ADC 3.3 V supply

VSS(PLL)

PLL ground

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